1. Field of the Invention
The present invention relates to a method of increasing the data-processing speed of a signal processor whose signal-processing unit, comprising at least one arithmetic logic unit and one multiplier, is fed with input data of n-bit word length.
2. Description of the Related Art
In "Electronik Zeitschrift", Vol. 35 (1986), September, No. 18, pages 112 to 125, the structure of signal processors is shown. Their signal-processing units comprises at least one arithmetic logic unit (ALU) and one multiplier. For different internal and external data bus systems and internal connections between the arithmetic logic unit and the multiplier, the article shows the input-data paths. The input-data paths are the paths to be traversed by the input data from their sources--internal or external memory devices such as read-only memories (ROMs) or random-access memories (RAMS)--to the inputs of the arithmetic logic unit (ALU) and/or the multiplier (MUL).
If such signal processors are supplied from a source with input-data words having a shorter word length than the maximum word length of n bits of the signal processor, the invalid bits must be masked during the loading process. This operation, just as bit manipulations with other maskings, can only be performed in the arithmetic logic unit of such a signal processor in a relatively time-consuming manner. Particularly, if input-data words for the multiplier are to be processed in this way, these input data must first be loaded into the arithmetic logic unit, then processed there, and then transferred to the input of the multiplier.
It is the object of the present invention to provide a method and apparatus whereby the data-processing speed of a signal processor is increased for such applications.